SR MTS Hardware RTL Development

Date Posted: 12/27/07

Looking for self-motivated, team oriented  hardware ASIC engineer to assume ownership to lead  development effort for an advanced programmable hardware engine.

Qualifications:

- Very good communication skills and ability to work with remote teams.

- Senior or Lead ASIC / Logic Design of a large ASIC, COT, system-on-a-chip, or full-custom VLSI chips with previous experience in Graphics, Video, Microprocessor Design, SOC,  or Multimedia ASIC design.

- Strong logic design and verification skills.

- Be proficient in all aspects of deep sub-micron/High Speed ASIC Design including but not limited to RTL coding, Synthesis (Design Compiler / Encounter) , verification, and Static Timing Analysis.

- Must have hands-on experience with Verilog, PLI, C/C++ programming, Perl and ASIC CAD tools (such as VCS, PrimeTime, Verplex).

- Programming skills in C and/or PERL.

- The ideal candidate will be familiar with all stages in the ASIC design flow including DFT, timing analysis, floorplanning, ECO flow, silicon bringup, and ATE test support.

- Ability to contribute during ASIC architecture, develop micro architectures and RTL design.

- Should have led/been part of successful tape-outs of at least 2-3 ASICs.

- Familiarity with back end/physical design challenges for complex ASICs.

- Well organized, methodical, and detail oriented.

Requirements:

Typically requires MSEE/CS combined with 5-7 years of related experience, or BSEE/CS combined with 7-10+ yrs related experience.

To apply, send your resume with stated career objectives to careers@elementcxi.com.